Multi-phase or multi-channel power conversion with current sharing control are commonly employed techniques for DC-DC power conversion in today's electronics (e.g. personal computer) market. Multi-phase power conversion provides a cost-effective power solution when load currents cannot be readily supported by single-phase converters. In a multi-phase system, the switching on of each channel is generally timed to be symmetrically out of phase with each of the other channels.
Conventional multiphase converters comprise a plurality of parallel connected regulators which each including pulse width modulation (PWM) modulators, each PWM modulator providing one phase for the converter. PWM modulators are generally each provided dedicated up-ramp and down-ramp signals and a pair of comparators for controlling pulse width. For example, for active pulse positioning (APP™) control for the multiphase PWM modulator 100 shown in FIG. 1, the rising edge of each phase PWM (PWM_1, PWM_2, etc.) output pulse trigger depending on its own dedicated down-ramp signal (VDOWN—RAMP), while the duty cycle of the pulse is determined by its own dedicated up-ramp signal (VUP—RAMP). The relationship between the up-ramp and the down-ramp signals is fixed as shown in FIG. 1. The down-ramps for the respective phases are determined by the system clock and are shifted relative to one another with a fixed phase angle. Therefore, there exists the possibility for a phase to miss one or more pulses during large repetitive load transients.
In FIG. 2, simulation results are shown for a multiphase converter based on the active pulse positioning (APP™) multiphase PWM modulator shown in FIG. 1. The upper panel shows the respective inductor currents for the various phases (I(L1), I(L2) and I(L3)), the center panel the respective phase output pulses (PWM_1, PWM_2 and PWM_3), and the lower panel the respective downramp waveforms (1, 2 and 3) together with the VCOMP signal from the error amplifier (not shown).
Due to the fixed relationship between the up-ramp and the down-ramp signals, one phase will miss a pulse if the COMP signal (VCOMP) from the error amplifier remains at levels below the valley point of the phases' down ramp, as shown in the circled regions in FIG. 2. As shown in FIG. 2, PWM-2 misses three (3) pulses.
Besides missed PWM pulses, under highly repetitive high frequency transient events, the turn-on time and duration of each phase PWM may vary significantly from cycle to cycle. Such variation can result in large dynamic imbalanced phase currents as shown in FIG. 3(a), which shows (from top to bottom) the respective inductor currents, the load current, and the respective PWM waveforms. FIG. 3(b) shows a zoom-in view of the same waveforms shown in FIG. 3(a).
This unbalanced phase current issue exists in all conventional pulse width modulation schemes, including trailing-edge, leading-edge or dual-edge modulators. In Robust Ripple Regulator, R3 TECHNOLOGY™, referred to herein as R3 control, a circuit architecture is provided which stabilizes current flow and reduces the time allowed between wave peaks in the regulator circuit. In R3™ control, there is a master clock block and several slave blocks. The master block generates and distributes a turn-on pulse to the slave blocks which creates PWM pulses. Because there is only one clock signal as the turn-on pulse, the turn-on pulse is sent to the slave blocks in a particular fixed firing order, such as: phase #1, #2, #3, #1 . . . . This arrangement can avoid the missing phase pulse problem described above, generally resulting in better dynamic current balance.
However, the current balance circuit in R3™-based designs provides a response that is a relatively low bandwidth to provide enhanced stability, which can keep the average phase current balanced. As a result, the R3™-response cannot generally solve the dynamic imbalanced phase current issue under highly repetitive high frequency transient events. The dynamic imbalanced phase current issue may cause very high instantaneous current in one phase, with huge negative current in another phase, and can cause damage or triggering of over-current protection circuitry. Dynamic imbalanced phase current is also known to reduce the power efficiency of the multi-phase regulator. What is needed is a new multi-phase regulator controller architecture and associated control methodology which provides improved dynamic current balance, particularly under highly repetitive high frequency transient events.